1. Field of the Invention
This invention relates to a resistance change memory device, specifically relates to data retention thereof in case a multi-level data storage scheme is adapted.
2. Description of the Related Art
Recently, it is noticed that a resistance change memory succeeds to a conventional flash memory. The “resistance change memory” described here includes not only a narrow-sensed resistance change memory (ReRAM: Resistance RAM), which has a recoding layer formed of a transition metal oxide for storing a resistance value state in a non-volatile manner, but also a phase change memory (PCRAM: Phase Change RAM), which uses a crystalline state (i.e., conductor) and an amorphous state (i.e., insulator) as data.
It is well known that there are two kinds of operation modes in ReRAMs as follows. One is referred to as a bipolar type of ReRAM, in which it is required of the applied voltage to be exchanged in polarity for switching the high resistance state and the low resistance state. The other is a unipolar type of ReRAM, in which the high resistance state and the low resistance state are settable by controlling the applied voltage value and applying time (for example, Y. Hosoi et al, “High Speed Unipolar Switching Resistance RAM (RRAM) Technology” IEEE International Electron Devices Meeting 2006 Technical Digest p. 793-796).
It is desirable to use a unipolar type of ReRAM to achieve a highly integrated memory cell array. In case of a unipolar type, stacking variable resistance elements and diodes at the cross points of bit lines and word lines, a cell array may be constituted without transistors. In addition, three-dimensionally stacking the cell arrays, it is possible to achieve a large capacitive memory (for example, see JP 2006-514393A (PCT/JP2003/003257)).
The data retention will be determined by the stability of the resistance state. For example, a high resistance state is defined as a reset state (i.e., thermally stabilized state) while a low resistance state is defined as a set state, and it becomes problematic that the set state easily shifts to the reset state side. That is, when a number of read operations are executed, the low resistance value of the set state gradually shifts toward the high resistance value side.
Note here, there is also such a case that the low resistance state is a stable state. In this case, the high resistance state easily shifts to the low resistance state. For example, in a PCRAM, the data retention on the high resistance state side usually becomes problematic.
The above-described data retention becomes a large problem specifically when a multi-level data storage scheme is adapted to the memory.